WSM_EX_EVENTS(3CPC) CPU Performance Counters Library Functions
NAME
wsm_ex_events - processor model specific performance counter events
DESCRIPTION
This manual page describes events specific to the following Intel CPU
models and is derived from Intel's perfmon data. For more information,
please consult the Intel Software Developer's Manual or Intel's perfmon
website.
CPU models described by this document:
+o Family 0x6, Model 0x2f The following events are supported:
arith.cycles_div_busy Cycles the divider is busy
arith.div Divide Operations executed
arith.mul Multiply operations executed
baclear.bad_target BACLEAR asserted with bad target address
baclear.clear BACLEAR asserted, regardless of cause
baclear_force_iq Instruction queue forced BACLEAR
bpu_clears.early Early Branch Prediciton Unit clears
bpu_clears.late Late Branch Prediction Unit clears
bpu_missed_call_ret Branch prediction unit missed call or return
br_inst_decoded Branch instructions decoded
br_inst_exec.any Branch instructions executed
br_inst_exec.cond Conditional branch instructions executed
br_inst_exec.direct Unconditional branches executed
br_inst_exec.direct_near_call Unconditional call branches executed
br_inst_exec.indirect_near_call Indirect call branches executed
br_inst_exec.indirect_non_call Indirect non call branches executed
br_inst_exec.near_calls Call branches executed
br_inst_exec.non_calls All non call branches executed
br_inst_exec.return_near Indirect return branches executed
br_inst_exec.taken Taken branches executed
br_inst_retired.all_branches Retired branch instructions (Precise Event)
br_inst_retired.conditional Retired conditional branch instructions (Precise Event)
br_inst_retired.near_call Retired near call instructions (Precise Event)
br_misp_exec.any Mispredicted branches executed
br_misp_exec.cond Mispredicted conditional branches executed
br_misp_exec.direct Mispredicted unconditional branches executed
br_misp_exec.direct_near_call Mispredicted non call branches executed
br_misp_exec.indirect_near_call Mispredicted indirect call branches executed
br_misp_exec.indirect_non_call Mispredicted indirect non call branches executed
br_misp_exec.near_calls Mispredicted call branches executed
br_misp_exec.non_calls Mispredicted non call branches executed
br_misp_exec.return_near Mispredicted return branches executed
br_misp_exec.taken Mispredicted taken branches executed
br_misp_retired.all_branches Mispredicted retired branch instructions (Precise Event)
br_misp_retired.conditional Mispredicted conditional retired branches (Precise Event)
br_misp_retired.near_call Mispredicted near retired calls (Precise Event)
cache_lock_cycles.l1d Cycles L1D locked
cache_lock_cycles.l1d_l2 Cycles L1D and L2 locked
cpu_clk_unhalted.ref_p Reference base clock (133 Mhz) cycles when thread is not halted
(programmable counter)
cpu_clk_unhalted.thread_p Cycles when thread is not halted (programmable counter)
cpu_clk_unhalted.total_cycles Total CPU cycles
dtlb_load_misses.any DTLB load misses
dtlb_load_misses.large_walk_completed DTLB load miss large page walks
dtlb_load_misses.pde_miss DTLB load miss caused by low part of address
dtlb_load_misses.stlb_hit DTLB second level hit
dtlb_load_misses.walk_completed DTLB load miss page walks complete
dtlb_load_misses.walk_cycles DTLB load miss page walk cycles
dtlb_misses.any DTLB misses
dtlb_misses.large_walk_completed DTLB miss large page walks
dtlb_misses.pde_miss DTLB misses caused by low part of address. Count also includes 2M
page references because 2M pages do not use the PDE.
dtlb_misses.stlb_hit DTLB first level misses but second level hit
dtlb_misses.walk_completed DTLB miss page walks
dtlb_misses.walk_cycles DTLB miss page walk cycles
ept.walk_cycles Extended Page Table walk cycles
es_reg_renames ES segment renames
fp_assist.all X87 Floating point assists (Precise Event)
fp_assist.input X87 Floating poiint assists for invalid input value (Precise Event)
fp_assist.output X87 Floating point assists for invalid output value (Precise Event)
fp_comp_ops_exe.mmx MMX Uops
fp_comp_ops_exe.sse_double_precision SSE* FP double precision Uops
fp_comp_ops_exe.sse_fp SSE and SSE2 FP Uops
fp_comp_ops_exe.sse_fp_packed SSE FP packed Uops
fp_comp_ops_exe.sse_fp_scalar SSE FP scalar Uops
fp_comp_ops_exe.sse_single_precision SSE* FP single precision Uops
fp_comp_ops_exe.sse2_integer SSE2 integer Uops
fp_comp_ops_exe.x87 Computational floating-point operations executed
fp_mmx_trans.any All Floating Point to and from MMX transitions
fp_mmx_trans.to_fp Transitions from MMX to Floating Point instructions
fp_mmx_trans.to_mmx Transitions from Floating Point to MMX instructions
ild_stall.any Any Instruction Length Decoder stall cycles
ild_stall.iq_full Instruction Queue full stall cycles
ild_stall.lcp Length Change Prefix stall cycles
ild_stall.mru Stall cycles due to BPU MRU bypass
ild_stall.regen Regen stall cycles
inst_decoded.dec0 Instructions that must be decoded by decoder 0
inst_queue_write_cycles Cycles instructions are written to the instruction queue
inst_queue_writes Instructions written to instruction queue.
inst_retired.any_p Instructions retired (Programmable counter and Precise Event)
inst_retired.mmx Retired MMX instructions (Precise Event)
inst_retired.total_cycles Total cycles (Precise Event)
inst_retired.x87 Retired floating-point operations (Precise Event)
io_transactions I/O transactions
itlb_flush ITLB flushes
itlb_miss_retired Retired instructions that missed the ITLB (Precise Event)
itlb_misses.any ITLB miss
itlb_misses.large_walk_completed ITLB miss large page walks
itlb_misses.walk_completed ITLB miss page walks
itlb_misses.walk_cycles ITLB miss page walk cycles
l1d.m_evict L1D cache lines replaced in M state
l1d.m_repl L1D cache lines allocated in the M state
l1d.m_snoop_evict L1D snoop eviction of cache lines in M state
l1d.repl L1 data cache lines allocated
l1d_cache_prefetch_lock_fb_hit L1D prefetch load lock accepted in fill buffer
l1d_prefetch.miss L1D hardware prefetch misses
l1d_prefetch.requests L1D hardware prefetch requests
l1d_prefetch.triggers L1D hardware prefetch requests triggered
l1d_wb_l2.e_state L1 writebacks to L2 in E state
l1d_wb_l2.i_state L1 writebacks to L2 in I state (misses)
l1d_wb_l2.m_state L1 writebacks to L2 in M state
l1d_wb_l2.mesi All L1 writebacks to L2
l1d_wb_l2.s_state L1 writebacks to L2 in S state
l1i.cycles_stalled L1I instruction fetch stall cycles
l1i.hits L1I instruction fetch hits
l1i.misses L1I instruction fetch misses
l1i.reads L1I Instruction fetches
l2_data_rqsts.any All L2 data requests
l2_data_rqsts.demand.e_state L2 data demand loads in E state
l2_data_rqsts.demand.i_state L2 data demand loads in I state (misses)
l2_data_rqsts.demand.m_state L2 data demand loads in M state
l2_data_rqsts.demand.mesi L2 data demand requests
l2_data_rqsts.demand.s_state L2 data demand loads in S state
l2_data_rqsts.prefetch.e_state L2 data prefetches in E state
l2_data_rqsts.prefetch.i_state L2 data prefetches in the I state (misses)
l2_data_rqsts.prefetch.m_state L2 data prefetches in M state
l2_data_rqsts.prefetch.mesi All L2 data prefetches
l2_data_rqsts.prefetch.s_state L2 data prefetches in the S state
l2_lines_in.any L2 lines alloacated
l2_lines_in.e_state L2 lines allocated in the E state
l2_lines_in.s_state L2 lines allocated in the S state
l2_lines_out.any L2 lines evicted
l2_lines_out.demand_clean L2 lines evicted by a demand request
l2_lines_out.demand_dirty L2 modified lines evicted by a demand request
l2_lines_out.prefetch_clean L2 lines evicted by a prefetch request
l2_lines_out.prefetch_dirty L2 modified lines evicted by a prefetch request
l2_rqsts.ifetch_hit L2 instruction fetch hits
l2_rqsts.ifetch_miss L2 instruction fetch misses
l2_rqsts.ifetches L2 instruction fetches
l2_rqsts.ld_hit L2 load hits
l2_rqsts.ld_miss L2 load misses
l2_rqsts.loads L2 requests
l2_rqsts.miss All L2 misses
l2_rqsts.prefetch_hit L2 prefetch hits
l2_rqsts.prefetch_miss L2 prefetch misses
l2_rqsts.prefetches All L2 prefetches
l2_rqsts.references All L2 requests
l2_rqsts.rfo_hit L2 RFO hits
l2_rqsts.rfo_miss L2 RFO misses
l2_rqsts.rfos L2 RFO requests
l2_transactions.any All L2 transactions
l2_transactions.fill L2 fill transactions
l2_transactions.ifetch L2 instruction fetch transactions
l2_transactions.l1d_wb L1D writeback to L2 transactions
l2_transactions.load L2 Load transactions
l2_transactions.prefetch L2 prefetch transactions
l2_transactions.rfo L2 RFO transactions
l2_transactions.wb L2 writeback to LLC transactions
l2_write.lock.e_state L2 demand lock RFOs in E state
l2_write.lock.hit All demand L2 lock RFOs that hit the cache
l2_write.lock.i_state L2 demand lock RFOs in I state (misses)
l2_write.lock.m_state L2 demand lock RFOs in M state
l2_write.lock.mesi All demand L2 lock RFOs
l2_write.lock.s_state L2 demand lock RFOs in S state
l2_write.rfo.hit All L2 demand store RFOs that hit the cache
l2_write.rfo.i_state L2 demand store RFOs in I state (misses)
l2_write.rfo.m_state L2 demand store RFOs in M state
l2_write.rfo.mesi All L2 demand store RFOs
l2_write.rfo.s_state L2 demand store RFOs in S state
large_itlb.hit Large ITLB hit
load_block.overlap_store Loads that partially overlap an earlier store
load_dispatch.any All loads dispatched
load_dispatch.mob Loads dispatched from the MOB
load_dispatch.rs Loads dispatched that bypass the MOB
load_dispatch.rs_delayed Loads dispatched from stage 305
load_hit_pre Load operations conflicting with software prefetches
longest_lat_cache.miss Longest latency cache miss
longest_lat_cache.reference Longest latency cache reference
lsd.active Cycles when uops were delivered by the LSD
lsd.inactive Cycles no uops were delivered by the LSD
lsd_overflow Loops that can't stream from the instruction queue
machine_clears.cycles Cycles machine clear asserted
machine_clears.mem_order Execution pipeline restart due to Memory ordering conflicts
machine_clears.smc Self-Modifying Code detected
macro_insts.decoded Instructions decoded
macro_insts.fusions_decoded Macro-fused instructions decoded
mem_inst_retired.loads Instructions retired which contains a load (Precise Event)
mem_inst_retired.stores Instructions retired which contains a store (Precise Event)
mem_load_retired.dtlb_miss Retired loads that miss the DTLB (Precise Event)
mem_load_retired.hit_lfb Retired loads that miss L1D and hit an previously allocated LFB
(Precise Event)
mem_load_retired.l1d_hit Retired loads that hit the L1 data cache (Precise Event)
mem_load_retired.l2_hit Retired loads that hit the L2 cache (Precise Event)
mem_load_retired.llc_miss Retired loads that miss the LLC cache (Precise Event)
mem_load_retired.llc_unshared_hit Retired loads that hit valid versions in the LLC cache (Precise
Event)
mem_load_retired.other_core_l2_hit_hitm Retired loads that hit sibling core's L2 in modified or unmodified
states (Precise Event)
mem_store_retired.dtlb_miss Retired stores that miss the DTLB (Precise Event)
mem_uncore_retired.local_hitm Load instructions retired that HIT modified data in sibling core
(Precise Event)
mem_uncore_retired.local_dram_and_remote_cache_hit Load instructions retired local dram and remote cache HIT data
sources (Precise Event)
mem_uncore_retired.remote_dram Load instructions retired remote DRAM and remote home-remote cache
HITM (Precise Event)
mem_uncore_retired.uncacheable Load instructions retired IO (Precise Event)
mem_uncore_retired.remote_hitm Retired loads that hit remote socket in modified state (Precise
Event)
misalign_mem_ref.store Misaligned store references
offcore_requests.any All offcore requests
offcore_requests.any.read Offcore read requests
offcore_requests.any.rfo Offcore RFO requests
offcore_requests.demand.read_code Offcore demand code read requests
offcore_requests.demand.read_data Offcore demand data read requests
offcore_requests.demand.rfo Offcore demand RFO requests
offcore_requests.l1d_writeback Offcore L1 data cache writebacks
offcore_requests_outstanding.any.read Outstanding offcore reads
offcore_requests_outstanding.any.read_not_empty Cycles offcore reads busy
offcore_requests_outstanding.demand.read_code Outstanding offcore demand code reads
offcore_requests_outstanding.demand.read_code_not_empty Cycles offcore demand code read busy
offcore_requests_outstanding.demand.read_data Outstanding offcore demand data reads
offcore_requests_outstanding.demand.read_data_not_empty Cycles offcore demand data read busy
offcore_requests_outstanding.demand.rfo Outstanding offcore demand RFOs
offcore_requests_outstanding.demand.rfo_not_empty Cycles offcore demand RFOs busy
offcore_requests_sq_full Offcore requests blocked due to Super Queue full
partial_address_alias False dependencies due to partial address aliasing
rat_stalls.any All RAT stall cycles
rat_stalls.flags Flag stall cycles
rat_stalls.registers Partial register stall cycles
rat_stalls.rob_read_port ROB read port stalls cycles
rat_stalls.scoreboard Scoreboard stall cycles
resource_stalls.any Resource related stall cycles
resource_stalls.fpcw FPU control word write stall cycles
resource_stalls.load Load buffer stall cycles
resource_stalls.mxcsr MXCSR rename stall cycles
resource_stalls.other Other Resource related stall cycles
resource_stalls.rob_full ROB full stall cycles
resource_stalls.rs_full Reservation Station full stall cycles
resource_stalls.store Store buffer stall cycles
sb_drain.any All Store buffer stall cycles
seg_rename_stalls Segment rename stall cycles
simd_int_128.pack 128 bit SIMD integer pack operations
simd_int_128.packed_arith 128 bit SIMD integer arithmetic operations
simd_int_128.packed_logical 128 bit SIMD integer logical operations
simd_int_128.packed_mpy 128 bit SIMD integer multiply operations
simd_int_128.packed_shift 128 bit SIMD integer shift operations
simd_int_128.shuffle_move 128 bit SIMD integer shuffle/move operations
simd_int_128.unpack 128 bit SIMD integer unpack operations
simd_int_64.pack SIMD integer 64 bit pack operations
simd_int_64.packed_arith SIMD integer 64 bit arithmetic operations
simd_int_64.packed_logical SIMD integer 64 bit logical operations
simd_int_64.packed_mpy SIMD integer 64 bit packed multiply operations
simd_int_64.packed_shift SIMD integer 64 bit shift operations
simd_int_64.shuffle_move SIMD integer 64 bit shuffle/move operations
simd_int_64.unpack SIMD integer 64 bit unpack operations
snoop_response.hit Thread responded HIT to snoop
snoop_response.hite Thread responded HITE to snoop
snoop_response.hitm Thread responded HITM to snoop
snoopq_requests.code Snoop code requests
snoopq_requests.data Snoop data requests
snoopq_requests.invalidate Snoop invalidate requests
snoopq_requests_outstanding.code Outstanding snoop code requests
snoopq_requests_outstanding.code_not_empty Cycles snoop code requests queued
snoopq_requests_outstanding.data Outstanding snoop data requests
snoopq_requests_outstanding.data_not_empty Cycles snoop data requests queued
snoopq_requests_outstanding.invalidate Outstanding snoop invalidate requests
snoopq_requests_outstanding.invalidate_not_empty Cycles snoop invalidate requests queued
sq_full_stall_cycles Super Queue full stall cycles
sq_misc.lru_hints Super Queue LRU hints sent to LLC
sq_misc.split_lock Super Queue lock splits across a cache line
ssex_uops_retired.packed_double SIMD Packed-Double Uops retired (Precise Event)
ssex_uops_retired.packed_single SIMD Packed-Single Uops retired (Precise Event)
ssex_uops_retired.scalar_double SIMD Scalar-Double Uops retired (Precise Event)
ssex_uops_retired.scalar_single SIMD Scalar-Single Uops retired (Precise Event)
ssex_uops_retired.vector_integer SIMD Vector Integer Uops retired (Precise Event)
store_blocks.at_ret Loads delayed with at-Retirement block code
store_blocks.l1d_block Cacheable loads delayed with L1D block code
cpu_clk_unhalted.thread_p Cycles thread is active
two_uop_insts_decoded Two Uop instructions decoded
uop_unfusion Uop unfusions due to FP exceptions
uops_decoded.esp_folding Stack pointer instructions decoded
uops_decoded.esp_sync Stack pointer sync operations
uops_decoded.ms_cycles_active Uops decoded by Microcode Sequencer
uops_decoded.stall_cycles Cycles no Uops are decoded
uops_executed.core_active_cycles Cycles Uops executed on any port (core count)
uops_executed.core_active_cycles_no_port5 Cycles Uops executed on ports 0-4 (core count)
uops_executed.core_stall_count Uops executed on any port (core count)
uops_executed.core_stall_count_no_port5 Uops executed on ports 0-4 (core count)
uops_executed.core_stall_cycles Cycles no Uops issued on any port (core count)
uops_executed.core_stall_cycles_no_port5 Cycles no Uops issued on ports 0-4 (core count)
uops_executed.port0 Uops executed on port 0
uops_executed.port015 Uops issued on ports 0, 1 or 5
uops_executed.port015_stall_cycles Cycles no Uops issued on ports 0, 1 or 5
uops_executed.port1 Uops executed on port 1
uops_executed.port2_core Uops executed on port 2 (core count)
uops_executed.port234_core Uops issued on ports 2, 3 or 4
uops_executed.port3_core Uops executed on port 3 (core count)
uops_executed.port4_core Uops executed on port 4 (core count)
uops_executed.port5 Uops executed on port 5
uops_issued.any Uops issued
uops_issued.core_stall_cycles Cycles no Uops were issued on any thread
uops_issued.cycles_all_threads Cycles Uops were issued on either thread
uops_issued.fused Fused Uops issued
uops_issued.stall_cycles Cycles no Uops were issued
uops_retired.active_cycles Cycles Uops are being retired
uops_retired.any Uops retired (Precise Event)
uops_retired.macro_fused Macro-fused Uops retired (Precise Event)
uops_retired.retire_slots Retirement slots used (Precise Event)
uops_retired.stall_cycles Cycles Uops are not retiring (Precise Event)
uops_retired.total_cycles Total cycles using precise uop retired event (Precise Event)
inst_retired.total_cycles_ps Total cycles (Precise Event)
SEE ALSO
cpc(3CPC) https://download.01.org/perfmon/index/illumos June 18, 2018 illumos